Download Defect and Fault Tolerance in VLSI Systems: Volume 1 by Israel Koren PDF

By Israel Koren

This booklet includes an edited number of papers provided on the foreign Workshop on disorder and Fault Tolerance in VLSI platforms held October 6-7, 1988 in Springfield, Massachusetts. Our thank you visit all of the participants and particularly the participants of this system committee for the tricky and time-consuming paintings interested by picking out the papers that have been awarded within the workshop and reviewing the papers integrated during this e-book. thank you also are as a result IEEE desktop Society (in specific, the Technical Committee on Fault-Tolerant Computing and the Technical Committee on VLSI) and the college of Massachusetts at Amherst for sponsoring the workshop, and to the nationwide technological know-how starting place for helping (under supply quantity MIP-8803418) the keynote deal with and the distribution of this publication to all workshop attendees. the target of the workshop used to be to carry t. ogether researchers and practition­ ers from either and academia within the box of illness tolerance and yield en­ ha. ncement in VLSI to debate their mutual pursuits in defect-tolerant architectures and versions for built-in circuit defects, faults, and yield. development during this zone was once bogged down by means of the proprietary nature of yield-related facts, and through the shortcoming of applicable boards for disseminating such details. The aim of this workshop was once consequently to supply a discussion board for a discussion and alternate of perspectives. A follow-up workshop in October 1989, with C. H. Stapper from IBM and V. ok. Jain from the collage of South Florida as normal co-chairmen, is being organized.

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Chinn, "Double-Bridge Test Structure for the evaluation of Type, Size and Density of Spot Defects", Technical Report CMUCAD-87-2, CMU (1987). 30. A. V. Ferris-Prabhu, "Yield Implications and Scaling Laws for Submicrometer Devices", IEEE Trans. Semiconductor Manufacturing, vol. I (2), pp. 449-61 (l988). 31. C. Kooperberg, "Circuit Layout and Yield", IEEE 1. Solid-State Circuits, vol. 23 (4), pp. 887-892 (1988). The defect sensitivity function gij and the term Pij introduced in this paper have the same meaning as the kernel K(x,w) and the fault probability (w) introduced in references 15, 24, and 25 above.

These unresolved difficulties invite the question as to whether it is possible to extract information about the size distribution of (potentially fatal) defects solely from yield data. Although yield models of increasing statistical sophistication are being developed, there is need for a better understanding of the physical bases underlying the statistical parameters contained in these models. There also does not appear to have been as much attention to the determin;ltion of defect size distributions and their relation to tools, technologies and environment.

Figure 5 shows a drawing of a 112 megabyte RAM on a six inch wafer. Pads and I/O locations are arranged down the center of the wafer to allow for ease of packaging using strip line, or flat lead. Table 3 shows the organization of this large RAM. The four layer metal structure utilizes a twelve square micron cell such as used in megabit and four megabit DRAMs. If smaller cells such as the four micron cells are used, larger DRAM capacity could be obtained. Table 4 shows the power, performance, and physical size of the wafer.

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